Computational tasks such as object and pattern recognition rely on deterministic learning in the brain carried out mostly at the synapses, which link the brain's neurons and shape the overall computational function of a group of neurons.¹ Modelers build mathematical abstractions of synaptic learning by approximating the behavior of biological synapses as they try to copy relevant processing functions.^2–4 Neuromorphic integrated circuits (ICs) implement transistor-based versions of these mathematical abstractions in order to realize adaptive, error-tolerant emulations of cognitive functions.^5,6

In recent years, there has been a steady increase in the size of neuromorphic systems in order to handle more advanced cognitive tasks. This calls for area-efficient circuit implementations, especially of synapses, since biology-derived topologies use far more synapses than neurons,⁷ which makes synapse size the determining factor in overall IC complexity.^6,8,9 While reducing synapse size, ideally the biological accuracy of the synapses' learning function should increase to keep pace with the biologists' and modelers' continuously refined understanding of cognitive functions.¹⁰ To date, these conflicting demands on the learning circuit's implementation have not received much attention. In particular, the usual two-step approach of deriving a mathematical model and subsequently building circuits for it tends to yield very complex circuits.^5,8 However, co-developing both the mathematical model and circuit implementation could balance both objectives, resulting in a circuit-optimized mathematical model that also exhibits good biological accuracy.

A synapse composes its learning function from the neurons' local-state variables.¹But most models of synaptic learning introduce synthetic dynamical variables driven by higher order information such as spike timings.^2,3,11 From a hardware perspective, implementing dynamical behavior—especially configurable time constants—consumes area. As a result, using local waveforms in the synaptic learning circuit would both closely mimic the biology and save area-expensive circuitry.

Our learning rule, called local-correlation plasticity (LCP), takes this approach, measuring the relationship between the activities of the triggering (presynaptic) and the receiving (postsynaptic) neurons of a synapse.¹²The activity of the postsynaptic neuron is naturally included in its membrane voltage u(t), which also has great influence on learning.^13,14 The presynaptic neuron's activity is visible to the synapse by a conductance change g(t) in the receiving neuron. Multiplying both variables results in the synaptic strength w¹²

Figure 1.

Principal operation of the local-correlation plasticity (LCP) learning rule, with conductance change g(t), membrane voltage u(t), and resulting synaptic weight (w) over the progress of time (t).

With our LCP learning rule, the number of dynamical variables can be minimized in the system design. The membrane voltage u(t) is generated by the neuron circuit and fed back to all connected synapses. Similarly, the waveform of the synaptic input g(t) needs to be generated only once per sending neuron. Thus, all waveform-generation circuits are separated from the individual synapse. This allows for a compact synapse circuit that essentially consists of a differential pair carrying out the difference computation and multiplication of equation (1).¹⁵ The waveform-sharing by the synapses fits nicely into the matrix structure used in neuromorphic chip design^6,8 (see Figure 2). Each synapse row connects to one postsynaptic neuron. A synapse column is driven by two input waveforms from which each synapse chooses one waveform.⁹This architecture provides sufficient flexibility for mapping typical network models⁹ while maximally reusing waveform-generation circuitry, thus making for an area-saving design. However, we wondered whether this approach could account for modern learning paradigms.

Optimized system architecture with extended configurability. Each synapse is able to choose between an externally driven presynaptic conductance change g(t)_{ext, i}, and one generated by internal feedback g(t)_{int, i} through an external/internal select bit. The presynaptic signals g(t)_i are scaled by the synaptic weight wⁱ_j, and their sum is fed to the respective postsynaptic neurons. U(t): membrane voltage (time).

One of the most influential models for synaptic learning, spike-timing-dependent plasticity (STDP),¹¹ accounts for the synaptic weight increase and decrease observed when applying a single spike of the pre- and postsynaptic neuron at fixed time intervals to the synapse.¹⁶ In the LCP rule, the timing dependencies arise naturally from the correlation between postsynaptic voltage and presynaptic conductance change, that is, the time windows are inherent in u(t) and g(t) (compare Figure 1). Figure 3 shows that a circuit implementation of the LCP rule,¹⁵ despite not being conceived specifically for STDP reproduction, can approximate the typical STDP window. It is also evident from Figure 3 that even, for Three Sigma manufacturing deviations, the STDP window only changes in its scaling, not its typical shape. This shows that our complexity-reducing approach results in a very robust learning implementation.

Simulation results for a spike-timing-dependent (STDP) protocol applied to a circuit realization of the LCP rule. The weight change is plotted over the time difference between an occurrence of a postsynaptic spike t_postand a presynaptic spike t_pre. Even for the complete range of statistical manifestations of the circuit parameters, the learning-time window is robustly replicated.

Recent computational analysis indicates that learning at the synapse is significantly more involved than a simple STDP dependency, so a generic third variable needed to be postulated.¹⁰ Experimental evidence also supports this postulate, with learning dependent on more complex spike orders,² on spike rate,¹⁴ or on alterations of the postsynaptic membrane voltage.^13,14 Figure 4 shows that the circuit realization of the LCP rule can replicate such a third variable. In this example, LCP replicates a pulse-triplet dependency with a high degree of biological veracity,² even though the single synapses are much simpler than typical STDP implementations.^5,8

Simulation results for a triplet protocol applied to the LDP rule circuit. The weight change is plotted as red/blue over the timing difference t₁ between the first triplet pulse and the middle pulse, and the difference t₂between the middle triplet pulse and the last pulse (see also insets on both sides). The triplet with two pre(synaptic) and one post(synaptic) spike is valid above the main diagonal. Below it, the triplet consists of two post and one pre pulse.

The synaptic learning expressed in our LCP rule combines high robustness and area efficiency in circuit terms with a biology-driven mathematical formulation. The LCP rule and its circuit realization can reproduce a wide range of complex biological learning phenomena^4,15 on a par with state-of-the-art, biology-oriented learning rules.^4,17 The circuit realization of the LCP rule is thus well suited to building large-scale neuromorphic systems with a much higher degree of biological accuracy than current approaches. We are involved with several neuromorphic hardware projects that provide an ideal substrate for applying the LCP rule to adaptive closed-loop interfaces to biological neural tissue or to biology-derived, very large scale integration information processing. Our future work will continue the co-development approach, especially modulation of the learning function (metaplasticity) of the LCP rule⁴ in the circuit realization.

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