From the very inception of the field of neuromorphic engineering, a significant part of the community focused its efforts on the development and implementation of arrays of silicon neurons for the rapid prototyping of neural networks. One of the first successful silicon neuron implementations was proposed by Mahowald and Douglas in the early nineties.¹ This circuit generated spikes that had striking similarities with the ones produced by real cortical neurons, as it implemented a 'conductance-based model’ that emulated the various ion currents responsible for producing nerve impulses. This approach, still being pursued by various groups today,^2–4 captures many details of how a real neuron works. However, it also requires the ability to successfully tune a large number of parameters, and typically takes up a large area of silicon real estate (due to a large number of transistors, large capacitors, or both).

Alternatively, a less sophisticated but smaller type of circuit design, is based on the integrate-and-fire (I&F) neuron model. This type of circuit, thanks to its smaller silicon-area requirements, has frequently been used both to implement large arrays of neurons on single chips, and in conjunction with the address-event-representation (AER) communication infrastructure, for transmitting spikes (events) among different chips. (This has been explained in the previous issue of the Neuromorphic Engineer⁵ and elsewhere.^6,7 One of the first implementations of an I&F neuron model was the 'axon-hillock’ circuit, originally proposed by Mead et al.⁸

Chip micrograph: the modification of a neuron-synapse-weights triplet occurs through the use of shift-registers.

Every year, the Neuromorphic Engineering workshop in Telluride, Colorado, allows scientists from many different disciplines and parts of the world to come together to discuss—and try to engineer—ideas into robotics and/or neural prostheses and other purposes. This year, four different chips were used for different tasks. One of these⁷ was an application-specific chip, requiring AER for communicating with the outside world. The other three chips^9–11 were more general-purpose integrate-and-fire neurons, where the first two used AER for communication with the outside world, and the second had an output for each neuron.

Here we focus on the last type of device (see Figure 1), the main purpose of which is to carry out several projects for implementing networks of I&F neurons with different (reconfigurable) types of architectures, operating in real time and able to interface with control signals for appropriate motor actuation. The chip, an evolution of a previous version,¹² is made up of ten integrate-and-fire neurons specifically designed to be used in a central pattern generator (CPG) configuration for locomotion of robotic bipeds. Each neuron has 19 synapses, of which eight allow external circuitry or sensory information to modify the output spike trains, ten allow each neuron to feed back to all the neurons on the chip, and one synapse is used to provide a tonic drive for the neurons. Each neuron-synapse pair can be set with an 8bit excitatory (or inhibitory) weight that modulates the currents charging (or discharging) the membrane capacitance. The chip can output spikes or pacemaker-type signals depending on the value set on the on-chip pulse width tuner. A refractory period modulator, finally, prevents the membrane capacitance from charging up for an amount of time dictated by the modulator. CPG-type signals can thus be created using the neurons as pacemaker cells or in a spiking configuration.

Two of the many possible central-pattern-generator networks implemented on the chip to allow the robot to walk in an open-loop system. The Snappy robot is also shown.

The key aspect of these signals is that they must be frequency-locked and out-of phase by any arbitrary degree.¹¹ In a typical human walking motion, for example, the hips are 180° out-of-phase between each other and the knees are 90° out-of-phase with the ipsilateral hip. Different gaits, in turn, require the limbs to have different phase relationships. The chip was used by the locomotion workgroup to create various such waveforms (see Figure 2), and tuned with appropriate weights to create a human-like walking gait for the Snappy robot, developed at Iguana Robotics, Inc.. Each motor on the robot's hips and knees requires direction and speed information to fix the robot's overall gait and velocity. To generate the direction signals for the motors, pacemaker neurons were set up to form the signals as described above, so all the outputs were frequency-locked and out-of-phase by appropriate amounts to achieve a quasi-human walking gait. The signals thus generated allowed the robot to be controlled open loop. Continuing efforts by various group members after the end of the workshop should soon be able to show that all four limbs can be properly controlled and with different gaits.

Locomotion Workgoup:

Project leaders were A. Cohen, R. Etienne-Cummings, and M. A. Lewis.

Project participants were R. Alvarez, C. Assad, K. Feller, J. Kutch, A. Horchler, K. Nakada, R. Reeve, J. Scrivens, M. Sekerli, F. Tenore, J. Tian, and L. Ting.

2. M. Mahowald and R. Douglas, A silicon neuron, Nature 354, pp. 515-518 26 November, 1991.
   
   
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4. M. F. Simoni, G. S. Cymbalyuk, M. E. Sorensen, R. L. Calabreseand and S. P. DeWeerth, A multi-conductance-silicon neuron with biologically matched dynamics, IEEE Trans. on Biomedical Engineering 51 (2), pp. 342-354 February, 2004.
   
   
5. E. Farquhar and P. Hasler, A bio-physically inspired silicon neuron, Proc. Int'l Symp. on Circuits and Systems 1, pp. 309-312 23-26 May, 2004.
   
   
6. R. J. Vogelstein, U. Mallik and G. Cauwenberghs, Beyond address-event communication: dynamically-reconfigurable spiking neural systems, The Neuromorphic Engineer 1 (1), pp. 1, 2004.
   
   
7. D. H. Goldberg, G. Cauwenberghs and A. Andreou, Analog VLSI spiking neural network with address domain probabilistic synapses, Proc. Int'l Symp. on Circuits and Systems 2, pp. 241-244 6-9 May, 2001.
   
   
8. P. Merolla and K. Boahen, A Recurrent Model of Orientation Maps with Simple and Complex Cells, Advances in Neural Information Processing Systems 16, pp. , 2004.
   
   
9. C. Mead, Analog VLSI and Neural Systems, Addison Wesley, 1989.
   
   
10. S. C. Liu and R. Douglas, Temporal coding in a silicon network of integrate-and-fire neurons, IEEE Trans. on Neural Networks 15 (5), pp. 1 September, 2004.
    
    
11. E. Chicca, G. Indiveri and R. Douglas, An event-based VLSI network of integrate-and-fire neurons, Proc. Int'l Symp. on Circuits and Systems 1, pp. 23-26 May, 2004.
    
    
12. F. Tenore, R. Etienne-Cummings and M. A. Lewis, Entrainment of silicon CentralPattern Generators for legged locomotory control, Advances in Neural Information Processing Systems 16, pp. 1, 2004.
    
    
13. M. A. Lewis, R. Etienne-Cummings, A. H. Cohen, M. Hartmann and Z. R. Xu, An in silico central pattern generator: silicon oscillator, coupling, entrainment, and physical computation, Biological Cybernetics 88, pp. 137-151, 2003.