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Silicon synapse implements multiple neural computational primitives
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Synapses are highly specialized structures that transmit information between neurons. When an action potential generated by a neuron reaches a presynaptic terminal, a cascade of events produces a flow of ionic currents into or out of the postsynaptic neuron's membrane, with a characteristic time course that can last up to several hundreds of milliseconds.1 Modeling the detailed dynamics of postsynaptic currents can be a crucial step for learning neural codes and encoding spatio-temporal patterns of spikes.2 However, both software computational models and VLSI (very large silicon integration) implementations of neural systems have often neglected the dynamic aspects of synaptic currents.
Modeling the temporal dynamics of each individual synapse in a network of integrate and fire (I&F) neurons can be very onerous in terms of silicon real-estate for dedicated VLSI implementations. A compromise between highly detailed models of synaptic dynamics and no dynamics at all is to use computationally efficient models that account for the basic macroscopic properties of synaptic transmission. We recently proposed a novel VLSI synaptic circuit, the differential-pair integrator (DPI),3 that implements one of these efficient models based on exponentials4 and supports a wide range of synaptic properties. The design of the DPI synapse was inspired by a series of similar circuits proposed in the literature: these collectively share many of the advantages of our solution but individually lack one or more of the features of our design.3
Figure 1 shows the schematic diagram of the silicon synapse. The basic DPI block reproduces the functionality of ligand-gated AMPA (α-amino-3-hydroxy-5-methylisoxazole-4- propionic acid) receptors. Assuming subthreshold operation and saturation regime, the transfer function of the circuit is a first order differential equation:
The differential equation is non-linear, however, when stimulated with an input step signal: in this case the DPI output current Isyn will rise to values such that Isyn≫Igain, if Iw≫ Iτ. In these conditions the Isyn dependence in the second term of Equation 1 cancels out, and the non-linear differential equation simplifies to the canonical first-order low-pass-filter equation:
The synaptic efficacy depends on both the current Iw and Igain. The presence of the Mw nFET (n-type field-effect transistor) makes the DPI compatible with previously proposed circuits for implementing synaptic plasticity, both on short time scales with models of short-term-depression5,6 (STD block in Figure 1), and on longer time scales with spike-based learning mechanisms, such as spike-timing-dependent-plasticity7 (STDP).
The thresholding property of the differential pair in the NMDA block of Figure 1 is used to reproduce the voltage gating property of NMDA receptors. Similarly the differential-pair in the G block is used to implement a linear dependence of the postsynaptic current on the difference between the postsynaptic membrane depolarization and the synapse reversal potential Vgthr, implementing conductance-based behaviour. A complementary version of the DPI circuit can be used to implement inhibitory GABAα (γ-aminobutyric acid) receptors.
An important additional computational primitive that can be implemented in the DPI, thanks to the extra synaptic efficacy parameter Igain is “homeostatic plasticity”.8 This slow adaptation mechanism is independent of spike-based learning rules that act on Vw. It can be used to reduce the intrinsic inhomogeneities of the VLSI circuits, thus improving the stability, robustness, and mismatch tolerance of VLSI networks of spiking neurons in the face of the tuning of circuits' parameters. Figure 2 shows the effect of changing Igain and Iw on the synaptic efficacy, as well as the effects of the NMDA and G blocks on the postsynaptic membrane potential.
In summary, we presented a new hardware model of synaptic dynamics that increases the similarities between silicon and biological synapses. The exponential time course of the postsynaptic currents implements linear synaptic summation, an essential property of synaptic transmission, observed in real neurons and used in computational models.4 Very simple additional circuits can extend the basic DPI functionality to include the phenomenological implementation of additional synaptic properties. Such circuits enrich the ensemble of computational primitives that can be emulated on silicon, in a unified framework that can encompass them all in a single compact circuit. When integrated in VLSI it is possible to implement massively-parallel and complex linear and non-linear synaptic-transmission computational primitives, and to carry out elaborate neural computational experiments in real-time.
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