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Charles Augustine at Intel's Circuit Research Laboratory in Hillsboro, Oregon, and a few of his colleagues unveil their design for a neuromorphic chip based on memristors and spin valves. Neurdons have heard this before...
A programmable chip can replace the ability of the cerebellum to learn a timed eye-blink response to a sound.
We present a high-speed communication infrastructure for a waferscale neuromorphic system, based on application-specific neuromorphic communication ICs in an field programmable gate arrays (FPGA)-maintained environment. The overall so-called pulse communication subgroup (ICs and FPGA) delivers a factor 25–50 more event transmission rate than other current neuromorphic communication infrastructures.
Complementary metal-oxide-semiconductor (CMOS) transistors are commonly used in very-large-scale-integration (VLSI) digital circuits as a basic binary switch that turns on or off as the transistor gate voltage crosses some threshold. Carver Mead first noted that CMOS transistor circuits operating below this threshold in current mode have strikingly similar sigmoidal current–voltage relationships as do neuronal ion channels and consume little power; hence they are ideal analogs of...
Epiphany, the Adapteva multicore processor, has been designed with the primary goal of accelerating applications in low-power devices such as smartphones and tablets, but also servers (in particular, to reduce monstrous power demands of large servers)...
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