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Advanced search Home  Applications » Power Workloadaware lowpower supply voltage controller PDF version  Permalink Current microprocessors are complex systems with multiple cores and nontrivial architectures, employing millions of sub100nm transistors designed for extreme power, speed, and reliability constraints.^{1} An efficient control scheme for dynamic power, reliability, error detectioncorrection, workload scheduling, and thermal management is required. However, neuromorphic architectures are currently more suitable for complex tasks, such as noisy nonlinear data classification and prediction, relative to Boolean logic architecture (see Figure 1). We use a dynamic voltage scaling (DVS) control scheme as a test bench to demonstrate neuromorphic controller efficiency.^{2} Figure 1. Microprocessors are typically designed to operate at a target frequency (f) and supply voltage (V_{DD}) for peak performance. Active power dissipation (P) in a complimentary metaloxidesemiconductor (CMOS) circuit is given by the equation P=CV_{DD}^{2}f, where C is total switched capacitance. However, peak performance is not always required, and significant energy savings can be achieved by dynamically varying the operating voltage and processor frequency to meet instantaneous workload demand. Most DVS schemes are implemented in software, which adopts offline profiling to learn average or worstcase execution task time.^{4} These schemes involve elaborate calculations to estimate a combination of V_{DD} and f optimized for minimum power, and are not suitable for timevarying workload. Two examples are a DVS controller that predicts future workload based on past workload profile using adaptive and nonadaptive filters,^{5} and statistical DVS techniques using cumulative distribution function (CDF) and probability density function (PDF) of offline workload profiling.^{6} Since the timevarying workload profile is highly nonlinear and aperiodic in nature, it is a good test bench to explore the potential of a neuromorphic controller predictor. Figure 2 shows the blocklevel diagram of a recurrent neuromorphic circuit that predicts future workload values based on past workload statistics. Input neurons store past workload values which are transmitted as input to the computation neuron. Based on synapse weights and bias, the computation neuron calculates the next workload value. The error generated by subtracting predicted and actual workload values is used to modify synaptic weights before the next prediction occurs. The analog version of the neuromorphic controller was implemented in 45nm CMOS using predictive technology model (PTM)^{7} files. The digital circuit was synthesized using OpenCell Standard Library in Synopsys Design Compiler. Figure 2. We use predicted workload to calculate the next V_{DD} for the microprocessor core. Hence, instead of using the conventional approach of scaling voltage after the workload value is known, workload prediction enables preemptive DVS. For testing neuromorphic circuit performance and prediction efficiency, workload values are mapped to three different supply voltages. When the predicted workload value crosses a threshold, the voltage is appropriately scaled. Figure 3 is a plot of actual and predicted workload by the analog and digital design. Workload values are further mapped to three V_{DD} levels of 0.9, 1.1, and 1.3V. Figure 3. The analog circuit consumes higher power during operation, but its primary advantage is nonlinear asynchronous operation. This renders it ideal as a generalpurpose, multipleinput, nonlinear microprocessor controller. The digital circuit occupies a larger area due to the large number of required gates to construct counters and comparators. We compared our predicted DVS voltage levels to that implemented in an Intel Core Duo Processor (T2400) running Linux OS and an ondemand DVS scheme.^{8} On average, the neuromorphic controller reduces total error by 50% and overestimation by approximately 32%, thereby yielding power savings. Conventional DVS techniques are typically implemented in software, and therefore a precise comparison between a neuromorphic controller and softwarebased schemes is nontrivial. Commerciallyavailable 45nm microprocessors typically possess power ratings in the 10–45W range. Thus, a neuromorphic controller implemented in hardware with a power dissipation overhead of 10–150μW, and greater prediction accuracy relative to softwarebased approaches, can be beneficial. References
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