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Workload-aware low-power supply voltage controller

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Saurabh Sinha, Jounghyuk Suh, Bertan Bakkaloglu, and Yu Cao

6 April 2011

Power dissipation is reduced by predicting future workload values and pre-emptively regulating supply voltage.

Current microprocessors are complex systems with multiple cores and non-trivial architectures, employing millions of sub-100nm transistors designed for extreme power, speed, and reliability constraints.1 An efficient control scheme for dynamic power, reliability, error detection-correction, workload scheduling, and thermal management is required. However, neuromorphic architectures are currently more suitable for complex tasks, such as noisy nonlinear data classification and prediction, relative to Boolean logic architecture (see Figure 1). We use a dynamic voltage scaling (DVS) control scheme as a test bench to demonstrate neuromorphic controller efficiency.2


(a) Qualitative plot of machine complexity vs. task complexity for a Boolean logic computer and a neuromorphic computing architecture.3 (b) Workload and dynamic voltage scaling (DVS, supply voltage) profile of a generic microprocessor. CPU: Central processing unit.

Microprocessors are typically designed to operate at a target frequency (f) and supply voltage (VDD) for peak performance. Active power dissipation (P) in a complimentary metal-oxide-semiconductor (CMOS) circuit is given by the equation P=CVDD2f, where C is total switched capacitance. However, peak performance is not always required, and significant energy savings can be achieved by dynamically varying the operating voltage and processor frequency to meet instantaneous workload demand.

Most DVS schemes are implemented in software, which adopts offline profiling to learn average- or worst-case execution task time.4 These schemes involve elaborate calculations to estimate a combination of VDD and f optimized for minimum power, and are not suitable for time-varying workload. Two examples are a DVS controller that predicts future workload based on past workload profile using adaptive and non-adaptive filters,5 and statistical DVS techniques using cumulative distribution function (CDF) and probability density function (PDF) of offline workload profiling.6 Since the time-varying workload profile is highly nonlinear and aperiodic in nature, it is a good test bench to explore the potential of a neuromorphic controller predictor.

Figure 2 shows the block-level diagram of a recurrent neuromorphic circuit that predicts future workload values based on past workload statistics. Input neurons store past workload values which are transmitted as input to the computation neuron. Based on synapse weights and bias, the computation neuron calculates the next workload value. The error generated by subtracting predicted and actual workload values is used to modify synaptic weights before the next prediction occurs. The analog version of the neuromorphic controller was implemented in 45nm CMOS using predictive technology model (PTM)7 files. The digital circuit was synthesized using Open-Cell Standard Library in Synopsys Design Compiler.


Block diagram of the spiking neuromorphic controller.

We use predicted workload to calculate the next VDD for the microprocessor core. Hence, instead of using the conventional approach of scaling voltage after the workload value is known, workload prediction enables pre-emptive DVS. For testing neuromorphic circuit performance and prediction efficiency, workload values are mapped to three different supply voltages. When the predicted workload value crosses a threshold, the voltage is appropriately scaled. Figure 3 is a plot of actual and predicted workload by the analog and digital design. Workload values are further mapped to three VDD levels of 0.9, 1.1, and 1.3V.


Workload prediction by the analog and digital circuits, and mapped supply voltages. VDD: supply voltage.

The analog circuit consumes higher power during operation, but its primary advantage is non-linear asynchronous operation. This renders it ideal as a general-purpose, multiple-input, non-linear microprocessor controller. The digital circuit occupies a larger area due to the large number of required gates to construct counters and comparators.

We compared our predicted DVS voltage levels to that implemented in an Intel Core Duo Processor (T2400) running Linux OS and an on-demand DVS scheme.8 On average, the neuromorphic controller reduces total error by 50% and over-estimation by approximately 32%, thereby yielding power savings.

Conventional DVS techniques are typically implemented in software, and therefore a precise comparison between a neuromorphic controller and software-based schemes is non-trivial. Commercially-available 45nm microprocessors typically possess power ratings in the 10–45W range. Thus, a neuromorphic controller implemented in hardware with a power dissipation overhead of 10–150μW, and greater prediction accuracy relative to software-based approaches, can be beneficial.




Authors

Saurabh Sinha
Arizona State University

Jounghyuk Suh
Arizona State University

Bertan Bakkaloglu
Arizona State University

Yu Cao
Arizona State University


References
  1. S. Rusu, S. Tam, H. Muljono, D. Ayers, J. Chang, R. Varada, M. Ratta and S. Vora, A 45nm 8-core enterprise Xeon processor, IEEE Asian Solid Sta., pp. 9-12 Nov., 2009. doi: 10.1109/ASSCC.2009.5357230

  2. S. Sinha, J. Suh, B. Bakkaloglu and Y. Cao, Workload-aware neuromorphic design of low-power supply voltage controller, Proc. 16th ACM/IEEE Int'l. Symp. Low Power Electron. Design, pp. 241-246, 2010. doi: 10.1145/1840845.1840896

  3. G. Cauwenberghs, Neuromorphic cognitive engineering: large-scale silicon neural systems, 4th Decade of the Mind Conf., 2009.

  4. X. Zhong and C.-Z. Xu, Energy-aware modeling and scheduling for dynamic voltage scaling with statistical real-time guarantee, IEEE Trans. Comput. 56, pp. 358-372, 2007. doi: 10.1109/TC.2007.48

  5. A. Sinha and A. Chandrakasan, Dynamic voltage scheduling using adaptive filtering of workload traces, Int'l. Conf. VLSI Design, pp. 221-226, 2001. doi: 10.1109/ICVD.2001.902664

  6. J. Lorch and A. Smith, PACE: a new approach to dynamic voltage scaling, IEEE Trans. Comput. 53, pp. 856-869, 2004. doi: 10.1109/TC.2004.35

  7. url: http://ptm.asu.edu (last accessed 28 Mar 2011)

  8. V. Pallipadi and A. Starikovskiy, The ondemand governor, Linux Symp., pp. 223-238, 2006.


 
DOI:  10.2417/1201104.003553

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