Welcome to The Neuromorphic Engineer
Tools » Design

Large-scale field-programmable analog arrays

PDF version | Permalink

Paul Hasler, Tyson S. Hall, and Christopher M. Twigg

1 March 2005

New devices may change the way engineers learn about and prototype neuromorphic circuits.

Reconfigurable hardware has long been of interest to circuit designers and engineers. In the digital domain, programmable logic devices (PLDs) have made a large impact on the development of custom digital chips by enabling the designer to try custom designs on easily-reconfigurable hardware. Since their conception in the late 1960s and early 1970s, PLDs have evolved into today's high-density field-programmable gate arrays (FPGAs).1 These are widely used in the lab for rapidly prototyping digital hardware, as well as in production goods to decrease time to market and to allow products to be easily upgraded after being deployed.


Digital PLDs (programmable logic devices) can be used to implement small, carefully-defined pieces of a complex system, while FPGAs (field-programmable gate arrays) can be used to implement entire systems including processor datapaths, complex digital signal processing functions, and more. Modern FPGAs can be 100-10,000 times larger and more complex than the PLDs of the1970s and1980s. Analagously, traditional FPAAs (field-programmable analog arrays) resemble early PLDs in that they are focused on small systems such as low-order filtering, amplification, and signal conditioning. However, the FPAAs based on floating-gate devices presented here are much larger devices, with the functionality needed to implement high-level system blocks in addition to having a large number of programmable op-amp and transistor elements.

However, reconfigurable analog hardware has been progressing much more slowly. While early analog integrated circuits (ICs) were often tunable with adjustable biases, truly reconfigurable analog circuitry in the form of field-programmable analog arrays (FPAAs) did not emerge until the late 1980s,2,3 and commercial offerings did not reach the market until 1996.4,5 Operational transconductance amplifier (OTA)-based FPAA designs have also been demonstrated,6,7 but, having been in the marketplace for nearly a decade, current FPAAs have struggled to establish a solid market base. They have been plagued by poor performance, small size, and a lack of generality/functionality.

Similar to the digital evolution from PLDs to FPGAs, FPAA chips are moving from these early stages to a large number of reconfigurable analog blocks. We recently introduced a new class of FPAA technology that resembles the architecture, large number of computing elements, functionality, and computational power of FPGA devices, while preserving the many orders of magnitude of power savings typical of analog signal processing.8,9 We typically refer to these devices as large-scale FPAAs (illustrated in Figure 1). These are accurately-programmable (through floating-gate approaches10) continuous-time analog devices that are capable of implementing full-scale analog signal processing systems. Fundamentally, FPAAs include two functions: routing (architecture) and computation. In our FPAA block, the switching device is an analog programmable element that can act as an ideal switch, variable resistor, current source, and/or configurable computational element in a single analog programmable memory element. Eliminating the switched banks of scaled devices typical in early FPAA designs creates a large savings in the area required for each computational analog block (CAB). In current CMOS technologies, one can envision thousands of CABs on a single IC, similar to the number of computational blocks for FPGAs. In minutes, a single FPAA device can be configured to implement several different circuit topologies that can be tested and compared. In addition, modern FPAAs can contain analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) that ease the interfacing of analog systems with digital logic implemented on FPGAs and/or microcontrollers.


Large-scale FPAA implementations. Examples of working compiled systems include sub-banding amplitude detectors, high-order ladder filters, and diffusor networks that make use of the routing fabric. Top: Die photograph of our first large-scale FPAA with 64 CABs (computational analog blocks), and over 150,000 analog programmable floating-gate devices in a 6×6mm area (0.35μm process). Bottom: The CAB design for this FPAA, based upon experimental results from smaller CAB arrays.9

Figure 2 shows one early instantiation of this element: a 64-block FPAA based around the CAB shown in Figure 1b, the functionality of which is enhanced by a mixture of medium- and coarse-grained computational blocks similar to many modern FPGA designs. These blocks were carefully selected to provide a sufficiently-flexible, generic architecture while optimizing certain frequently-used signal-processing blocks. The high-level CABs used in this design consist of a capacitively-coupled current conveyor (C4) used as a bandpass filter module, a peak detector, and the 4×4 vector-matrix multiplier block. In general, the C4 module provides a straightforward method of sub-banding an incoming signal. This allows Fourier analysis analogous to performing a fast Fourier transform (FFT) in the digital domain. The vector-matrix multiplier block allows the user to perform a matrix transformation on the incoming signals.

FPAAs introduce new opportunities to improve analog circuit design and signal processing education. By providing students with an easily reconfigurable, general-purpose analog device, laboratory projects can grow in scope and functionality. FPAAs are a natural fit in analog circuit courses, either in basic or more-advanced circuits courses, allowing students to use FPAAs to implement and test multiple circuit designs within a single laboratory period.

When these FPAA chips become available, we envision them impacting the teaching of neuromorphic IC circuits, the design efforts of early neuromorphic IC research, and the design of larger neuromorphic testbeds. The number of exploratory IC fabrication runs should be significantly reduced, particularly when investigating effects not well modelled by simulation tools. Initial teaching in neuromorphic IC design might no longer require training students to be proficient at IC layout or building custom test setups to show system functionality, but rather focus on the concepts being investigated. Eventually, custom ICs can be derived from the corresponding experimental results. FPAAs could expand to a set of ICs that include specialized blocks including a reconfigurable set of biological channels and synapses,11 front-end cochlea models, on-chip sensors (e.g. pixel arrays for vision applications), and specialized digital interfaces (i.e. address-event representation).




Authors

Paul Hasler
Georgia Institute of Technology

Tyson S. Hall
Southern Adventist University

Christopher M. Twigg
Georgia Institute of Technology


References
  1. P. Chow, S. O. Seo, J. Rose, K. Chung, G. Paez-Monzon and I. Rahardja, The design of an SRAM-based field-programmable gate array-part I: architecture, IEEE Trans. on Very Large Scale Integration (VLSI) Systems 7 (2), pp. 191-197 June, 1999.

  2. M. A. Sivilotti, Wiring Considerations in Analog VLSI Systems, with Application to Field-Programmable Networks (VLSI), California Institute of Technology, Pasadena, CA, 1991. Ph.D. thesis.

  3. P. G. Gulak, Field-programmable analog arrays: past, present and future perspectives, IEEE Region 10 Int'l Conf. on Microelectronics and VLSI, pp. 123-126 November, 1995.

  4. David Marsh, Programmable analogue ICs challenge spice-and-breadboard designs, EDN Europe, pp. 30-36 October, 2001. Reed Business Information http://www.ednmag.com

  5. Totally reconfigurable analog circuit-TRAC R March, 1999. Fast Analog Solutions Ltd. http://www.zetex.com

  6. B. Ray, P. P. Chaudhuri and P. K. Nandi, Design of OTA based field programmable analog array, Proc. 13th Int'l Conf. on VLSI Design, pp. 494-498 January, 2000.

  7. B. Pankiewicz, M. Wojcikowski, S. Szczepanski and Y. Sun, A field programmable analog array for CMOS continuous-time OTA-Cfilter applications, IEEE J. Solid-State Circuits 37 (2), pp. 125-136 Febuary, 2002.

  8. T. Hall, D. Anderson and P. Hasler, Field-Programmable Analog Arrays: A floating-gate Approach, 12th Int'l Conf. on Field Programmable Logic and Applications, Montpellier, France September, 2002.

  9. T. S. Hall, C. M. Twigg, P. Hasler and D. V. Anderson, Application performance of elements in a floating- gate FPAA, Proc. 2004 IEEE Int'l Symp. on Circuits and Systems, pp. 589-592 May, 2004.

  10. M. Kucic, A. Low, P. Hasler and J. Neff, A programmable continuous-time floating-gate Fourier processor, IEEE Trans. on Circuits and Systems II 48 (1), pp. 90-99 January, 2001.

  11. E. Farquhar, D. Abramson and P. Hasler, A Reconfigurable Bidirectional Active 2-Dimensional Dendrite Model, Int'l Symp. on Circuits and Systems Vancouver, 2004.


 
DOI:  10.2417/1200503.0017

@NeuroEng



Tell us what to cover!

If you'd like to write an article or know of someone else who is doing relevant and interesting stuff, let us know. E-mail the editor and suggest the subject for the article and, if you're suggesting someone else's work, tell us their name, affiliation, and e-mail.