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A bias-current-generators toolkit
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Analog or mixed-signal CMOS chips usually require a number of fixed reference currents for biasing amplifiers, determining time constants and pulse widths, powering loads for static logic, and so forth. The required currents can span a wide range: if the dynamics of the circuits span timescales from nanoseconds to seconds, for instance. Often, in experimental chips, these references are left out because designers assume that these ‘standard’ circuits could be easily added in a later revision. As a result, chips are designed that must be individually tuned for correct operation with a multitude of external pots to set gate voltages. The required voltages, unfortunately, depend on chip-to-chip variation in threshold voltage, and secondary users must be tutored on the tuning of the parameters. Moreover, the very-small bias currents that are often needed in these chips are problematic to generate externally.
We have developed a toolkit that allows the designer to automatically generate the schematics and layout of a bias generator circuit, using the Tanner EDA tools.1 The bias generator derives a wide-ranging set of fixed bias currents from a single master, and the desired bias currents are specified in the schematic, using parameter cells. A compiler parses the netlist from the schematic, computes the range of biases, the number of required splitter cells, and the master bias current. It then builds the layout of the complete generator using a set of predefined cells combined with generated routing. The cells are constructed to be used with MOSIS-scalable λ-based design rules, with two metal single-poly processes.
The circuit shown in Figure 1 generates the bias currents, all of which are produced by dividing down a single master current Im using a current-splitter network. These smaller currents can then be copied or scaled with current mirrors, or passed through a differential pair to provide a variable bias in a particular current range.
The master current Im is generated by the familiar bootstrapped current reference attributed to Widler and first reported in CMOS by Vittoz et al.2 Transistors Mn1 and Mn2 have a gain ratio (Wn1/Ln1)/(Wn2/Ln2)=M. Since the currents in the two branches are forced to be the same by the mirror Mp1-Mp2, the Mn current density ratios set up a difference in their gate-source voltage, which is expressed across the load R. Resistance R and ratio Ai determine the current. The master current Im—which flows in the loop—is computed by equating the currents in the two branches. In subthreshold, this yields the remarkably simple yet accurate formula:
With ideal transistors, Im does not depend on the supply or threshold voltages, but is monotonic in temperature (approximately PTAT, proportional to absolute temperature, in subthreshold). In reality, it is slightly affected by the supply voltage through drain conductance, and also by mismatch of the threshold voltage and β between the transistors in the current mirrors.
The ratio M is not critical as long as it is substantially larger than 1. We have used values from 20 to 120. A very large ratio can destabilize the circuit through the parasitic capacitance CR on VonVR. A common error in this circuit is to have too much capacitance to ground at VR; this excessive capacitance causes large-signal limit-cycle oscillations. The circuit can be stabilized by making the compensation capacitor Cn several times CR. In practice, we usually bring out Vn to ensure that the master bias can be stabilized.Table 1.
A startup circuit is necessary to avoid the stable zero-current operating point. Transistors Mk1, Mk2, M pd, and MOS capacitors Ck1 and Ck2 enable the startup and power control functionality. Vpd allows for soft power control and is tied to ground for normal operation. Raising Vpd to Vdd turns off the master bias and the derived biases, and returning Vpd to ground turns the bias generator back on.
The master current is copied to a Bult and Geelen3 current splitter and divided successively by it to form a geometrically-spaced series of smaller currents. At each branch, a fixed fraction of the current is split off, while the rest continues to later stages. The last stage is sized to terminate the line as though it were infinitely long. The current splitter principle accurately splits currents over all operating ranges from weak to strong inversion, independent of everything but the effective device geometry. Figure 1 shows an R-2R splitter—built from unit transistors—that splits by octaves. The splitter has N stages; the current at the kth stage is Im/2k.
We have used these bias generators in several generations of CMOS process technology (1.6μm, 0.8μm, and 0.35μm) with no striking differences in performance. Here we show a result from a bias generator with a 20-stage octave splitter built in a 0.35μm process using the design kit. Figure 2 shows the measure output currents of the octave splitter biased with a single generated master bias current of 10μA. It is amazingly ideal over 20 octaves (six decades) spanning strong to weak inversion. A current of 10pA is reliably generated from a master current of 10μA. For more details of the bias generator, the design kit, and measurements, readers are referred to in the references.1,4
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