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Word-serial address-event representation workshop
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Since the beginning of neuromorphic VLSI, designers have been grappling with the problem of transmitting thousands of neural signals on and off chips. Starting with the pioneering work of Sivilotti and Mahowald, the research community has largely stuck with an asynchronous event-driven interface where a silicon neuron's digital address is transmitted when it spikes. As such, log2(N) shared wires replace N dedicated wires. These address-events, as they are called, utilize the speed of metal wires, which is wasted when a wire is dedicated to a single neuron. Sharing bandwidth this way enables larger neural networks to be built. Also, address-events can be rerouted, whereas metal wires cannot. While most of the improvements in this approach have focused on mechanisms for routing and broadcasting spikes between chips and computers, little has changed in the actual protocol.
Until recently, the existing protocol could not be expanded to handle systems with multiple senders and receivers without adding significant external circuitry because this decade-old technique did not distinguish one chip from another. The Boahen lab at the University of Pennsylvania created a new protocol that addresses this limitation. The word-serial address-event representation (AER) appends chip addresses to the neuron's row and column addresses, all of which are transmitted sequentially, thereby distinguishing events from different chips. In addition to being expandable, word-serial is efficient: it cuts the number of address lines in half.
While creating a new protocol for communication that is expandable is an academic achievement, it only becomes useful if it is adopted by many users. To promote this new approach and facilitate its adoption, we obtained financial support from INE and organized a short, focused workshop to train students and faculty on the word-serial AER concept and on automated tools for its implementation. We also received a generous donation of computer-aided-design software (Tanner Tools Pro) from Tanner Research. After soliciting applications from advanced students and interested faculty, we selected a group to meet 1-5 December, 2005 at the University of Pennsylvania campus in Philadelphia. INE paid the travel expenses of domestic applicants and the lodging expenses of all non-faculty workshop participants at a hotel on campus. A conference room on campus was filled with rented computer systems loaded with the Tanner Tools Pro package and the Boahen Lab's chip-design tools. In addition to the organizers, we enlisted the help of two dedicated teaching assistants: Joseph Lin and Paul Merolla, both from the Boahen Lab.
The primary goal of our workshop was to have participants leave with the finished layout of a chip design that incorporates a core circuit from their particular research area into a word-serial AER transmitter and/or receiver frame. All designs were to be compatible with the L-Edit software suite upon arrival. While this was a burden for some participants, it was the only practical way to ensure a completed chip in three days.
One important component of the workshop was the requirement that every participant arrive having read the tutorial document and with a completed pixel layout, plus schematics. Joseph Lin was assigned to pester everyone two weeks ahead of time to send in their layout and schematics so that he could check them. We asked everyone to give a 10 minute talk at the beginning of the workshop to present their pixel design and explain what their overall plan was for a chip. On the first day, Joseph Lin gave a short lecture on the ChipGen tool for compiling AER chips developed in the Boahen Lab. Kwabena Boahen gave two lectures describing the evolution of the particular transceiver implementation that ChipGen was compiling and the types of output the fabricated chip would produce. He also presented a vision for the future of AER and multichip neuromorphic systems.
Projects brought by the participants included: a 2D current-mode cochlea with AER neurons; an ultrasonic cochlea with a 2D array of AER neurons; a high-resolution avalanche diode array imager; a 2D neuron transceiver chip; a contact imager for detecting the location of cell shadows; a spiking neuron imager with correlated double-sampling; and a 2D change-detection retina that signals using AER spikes.
Because of the workshop's short length, accomplishing our goals required dedication, as well as prior preparation. While we were proactive in urging that everyone arrive prepared, it was difficult to anticipate the miscommunication and confusion on certain aspects of ChipGen's operation, a result of insufficient detail in the documentation we provided. We resolved these questions at the workshop, but precious time was lost.
Overall, the workshop was a great opportunity for intense interaction with students interested in utilizing ChipGen, and for discussions of the needs of various users from labs around the world. Participant feedback was quite positive, and continuing discussion on a blog or website was the most-commonly expressed desire. We feel that our community needs many more workshops of this kind, by various experts on different topics, and that this type of intense, goal-oriented workshop provides both camaraderie and inspiration that generate excitement.
Tara Hamilton, University of Sydney, Australia
Hisham Ahmed Abdalla, University of Maryland, MD
Srinjoy Mitra, Institute for Neuroinformatics, ETH, Switzerland
Miriam Marwick, Johns Hopkins University, MD
Beatriz Olleta, Johns Hopkins University, MD
David Sander, University of Maryland, MD
Alfred Haas, University of Maryland, MD
Mike Chi, Johns Hopkins University, MD
Zhengming Fu, Yale University, CT
Andreas Andreou, Johns Hopkins University, MD
Eugenio Culurciello, Yale University, CT
Viktor Gruev, University of Pennsylvania, PA
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